8051 Core Specification

8-bit CPU optimized for control applicationsExtensive Boolean processing (single-bit logic) capabilities64K Program Memory address space64K Data Memory address spaceUp to 4K bytes of on-chip Program Memory128 bytes of on-chip Data RAM32 bi-directional and individually addressable I/O linesTwo 16-bit timer/counters6-source/5-vector interrupt structure with two priority levels
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8051 Core Specification 8051CoreSpecification Outlines Introduction Architecture Operation Registers Introduction MCS51family,originallydesignedbyIntelin the1980’s Usedinalargepercentageofembedded systems Includesseveralonchipperipherals,like timersandcounters 128bytesofonchipdatamemoryandupto 4Kbytesofonchipprogrammemory Features(1/2) 8bitCPUoptimizedforcontrolapplications ExtensiveBooleanprocessing(singlebitlogic)capabilities 64KProgramMemoryaddressspace 64KDataMemoryaddressspace Upto4KbytesofonchipProgramMemory 128bytesofonchipDataRAM 32bidirectionalandindividuallyaddressableI/Olines Two16bittimer/counters 6source/5vectorinterruptstructurewithtwoprioritylevelsFeatures(2/2) Outlines Introduction Architecture Operation Registers Architecture MemoryOrganization CPUClock InterruptStructure PortStructures Timer/Counters Reset MemoryOrganization(1/3) Logicalseparationofprogramanddatamemory  SeparateaddressspacesforProgram(ROM)andData (RAM)Memory  AllowDataMemorytobeaccessedby8bitaddresses quicklyandmanipulatedby8bitCPU ProgramMemory  Onlyberead,notwrittento  Theaddressspaceis16bit,somaximumof64Kbytes  Upto4Kbytescanbeonchip(internal)of8051core  PSEN(ProgramStoreEnable)isusedforaccessto externalProgramMemory MemoryOrganization(2/3) DataMemory  Includes128bytesofonchipDataMemorywhich aremoreeasilyaccessibledirectlybyits instructions  ThereisalsoanumberofSpecialFunction Registers(SFRs)  InternalDataMemorycontainsfourbanksofeight registersandaspecial32bytelongsegmentwhich isbitaddressableby8051bitinstructions  Externalmemoryofmaximum64Kbytesis accessibleby“movx” MemoryOrganization(3/3) InternalDataMemory,128bytes CPUClock 8051microcontrollerhasaclockinputpin InterruptStructure The8051provides4interruptsources  Twoexternalinterrupts  Twotimerinterrupts AdditionaldescriptionfollowsinOperations chapter PortStructures(1/3) The8051containsfourI/Oports Allfourportsarebidirectional EachporthasSFR(SpecialFunctionRegisters P0throughP3)whichworkslikealatch,an outputdriverandaninputbuffer BothoutputdriverandinputbufferofPort0 andoutputdriverofPort2areusedfor accessingexternalmemory PortStructures(2/3) Accessingexternalmemoryworkslikethis  Port0outputsthelowbyteofexternalmemory address(whichistimemultiplexedwiththebyte beingwrittenorread)  Port2outputsthehighbyte(onlyneededwhenthe addressis16bitswide) PortStructures(3/3) Port3pinsaremultifunctional Thealternatefunctionsareactivatedwiththe1 writteninthecorrespondingbitintheport SFRReadModifyWriteFeature(1/2) Whenreadingaportsomeinstructionsread thelatchandothersreadthepin Theinstructionsthatreadthelatchratherthan thepinaretheonesthatreadavalue(possibly changeit),anthenrewriteittothelatchare called“readmodifywrite”instructionsReadModifyWriteFeature(2/2) Timer/Counters The8051hastwo16bitTimer/Counter registers  Timer0  Timer1 Bothcanworkeitherastimersorevent counters Bothhavefourdifferentoperatingmodesfrom whichtoselect(allmodesaredescribedin Operationschapter) Reset TheresetinputistheRSTpin Outlines Introduction Architecture Operation Registers