ADVANCED TỔNG HỢP CHIP ASIC.

UNIX is a registered trademark of UNIX Systems Laboratories, Inc. Verilog is a registered trademark of Cadence Design Systems, Inc. RSPF and DSPF is a trademark of Cadence Design Systems, Inc. SDF and SPEF is a trademark of Open Verilog International. Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! are registered trademarks of Synopsys, Inc. Design Analyzer, Design Vision, Physical Compiler, Design Compiler, DFT Compiler, VHDL Compiler, HDL Compiler, ECO Compiler, Library Compiler, Synthetic Libraries, DesignTime, Floorplan Manager, characterize, dont_touch, dont_touch_network and uniquify, are trademarks of Synopsys, Inc....
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ADVANCED TỔNG HỢP CHIP ASIC.ADVANCED ASIC CHIP SYNTHESIS Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® SECOND EDITIONTrademark InformationUNIX is a registered trademark of UNIX Systems Laboratories, Inc.Verilog is a registered trademark of Cadence Design Systems, Inc.RSPF and DSPF is a trademark of Cadence Design Systems, Inc.SDF and SPEF is a trademark of Open Verilog International.Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! areregistered trademarks of Synopsys, Inc.Design Analyzer, Design Vision, Physical Compiler, Design Compiler, DFTCompiler, VHDL Compiler, HDL Compiler, ECO Compiler, Library Compiler,Synthetic Libraries, DesignTime, Floorplan Manager, characterize, dont_touch,dont_touch_network and uniquify, are trademarks of Synopsys, Inc.SolvNET is a service mark of Synopsys, Inc.All other brand or product names mentioned in this document, are trademarks orregistered trademarks of their respective companies or organizations.All ideas and concepts provided in this book are authors own, and are not endorsedby Synopsys, Inc. Synopsys, Inc. is not responsible for information provided in thisbook. ADVANCED ASIC CHIP SYNTHESIS Using Synopsys® Design Compiler™Physical Compiler™ and PrimeTime® SECOND EDITION Himanshu Bhatnagar Conexant Systems, Inc. KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOWeBook ISBN: 0-306-47507-3 0-7923-7644-7Print ISBN:©2002 Kluwer Academic PublishersNew York, Boston, Dordrecht, London, MoscowPrint ©2002 Kluwer Academic PublishersDordrechtAll rights reservedNo part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the PublisherCreated in the United States of AmericaVisit Kluwer Online at: http://kluweronline.comand Kluwers eBookstore at: http://ebooks.kluweronline.com To my wife Niveditaand my daughter NayanContents xvForewordPreface xviiAcknowledgements xxiiiAbout The Author xxvCHAPTER 1: ASIC DESIGN METHODOLOGY 1 Traditional Design Flow1.1 2 Specification and RTL Coding1.1.1 4 Dynamic Simulation1.1.2 5 Constraints, Synthesis and Scan Insertion1.1.3 6 Formal Verification1.1.4 8 10 Static Timing Analysis using PrimeTime1.1.5 Placement, Routing and Verification1.1.6 11 Engineering Change Order1.1.7 12 Physical Compiler Flow1.2 131.2.1 Physical Synthesis 16 Chapter Summary1.3 17viii 19CHAPTER 2: TUTORIAL2.1 20 Example Design Initial Setup 212.2 22 Traditional Flow2.3 22 Pre-Layout Steps2.3.1 Post-Layout Steps 362.3.2 Physical Compiler Flow2.4 42 Chapter Summary 422.5CHAPTER 3: BASIC CONCEPTS 45 Synopsys Products3.1 45 Synthesis Environment3.2 48 Startup Files3.2.1 48 System Library Variables3.2.2 49 Objects, Variables and Attributes3.3 51 Design Objects3.3.1 51 Variables3.3.2 52 Attributes3.3.3 53 Finding Design Objects3.4 54 Synopsys Formats3.5 55 Data Organization3.6 55 Design Entry3.7 56 Compiler Directives3.8 57 HDL Compiler Directives3.8.1 58 VHDL Compiler Directives3.8.2 60 Chapter Summary3.9 61CHAPTER 4: SYNOPSYS TECHNOLOGY LIBRARY 634.1 64 Technology Libraries4.1.1 Logic Library 64 Physical Library4.1.2 64 Logic Library Basics4.2 65 Library Group4.2.1 654.2.2 Library Level Attributes 66 Environment Description4.2.3 66 Cell Description4.2.4 71 Delay Calculation4.3 74 Delay Model4.3.1 74Contents ix4.3.2 Delay Calculation Problems ...