analog bicmos design practices and pitfalls phần 4

Trong khi các giá trị tuyệt đối của các thông số thiết bị là khó khăn để duy trì, hai thiết bị có thể được chính xác phù hợp trong một mạch. Mạch này cho phép thiết kế kỹ thuật được sử dụng mà kết quả trong các chức năng chính xác. Trong phần này, chip bố trí cho phù hợp với chính xác của các thành phần thảo luận.
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analog bicmos design practices and pitfalls phần 4now to Figure 3.1b. Here, we have placed a second transistor such thatVbe (Q2) = Vbe (Q1). If we assume that Q1 and Q2 are identical in allrespects, then Is (Q1) = Is (Q2), and ultimately Ic (Q2) = Ic (Q1). Thisis the basic principle of operation for a current mirror.Example Using the circuit from Figure 3.1b, find the collector current in tran-sistor Q2 if R1 = 10 k Ω. Use VCC = 5 V, Is = 200E − 18 A andVT = 26 mV . Assume ideal NPN transistors with β = ∞. Using the approximation Vbe = 0.7V , solve for Ic (Q1): 5 − 0.7 Ic (Q1) = = 430 µA 10, 000 Find the “real” Vbe value: 430E − 6A Vbe = 26mV ln = 738.3 mV 200E − 18A Recalculate the current: 5 − 0.7383 Ic (Q1) = = 426.2 µA 10, 000 Recalculate V be: 426.2E − 6A Vbe = 26mV ln = 738.1 mV 200E − 18A Another iteration may be made, but the change in current betweeniterations was only 1%. This level of refinement is usually good enoughfor first-pass design. Based on our assumption that both transistors areideal, we can conclude that the collector current in Q2 is equal to thatin Q1 and so Ic (Q2) = Ic (Q1) = 426.2 µA. We can expand this analysis to multiple transistors. Consider thecircuit in Figure 3.2a. This circuit has two mirror transistors. Usingthe same assumptions of ideality and identical transistors, we come tothe conclusion that each mirror transistor is sinking current equal to thereference current. Furthermore, if we tie the collectors of both mirrortransistors together, the output current of the mirror is equal to twicethe reference current, as shown in Figure 3.2b. This leads to an interesting point. What happens if transistors Q2 andQ3 are merged into a single device? Making the emitter size twice asbig as in Q1 can do this. The correct answer is that the output currentof the “2X” mirror will be twice the reference current. Accuracy of theFigure 3.2 Multiple transistor current mirror.Figure 3.3 NPN current mirror layout. Blue indicates shallow-n+ dop-ing for emitter and collector ohmic contact. Green indicates shallow-p base.White indicates contact openings. Light yellow indicates n- epitaxial layer.mirror will depend on the physical layout of the transistors. Figure 3.3shows two options for “2X” layout. For current multiplication by an integer value, mirror 2 will be moreaccurate. This is because layout and fabrication gradients should affectthe base-emitter junctions of the reference and mirror 2 in a similarmanner. Effects on mirror 1 will be somewhat different. However, forcurrent multiplication by a fractional value, say 1.5X, mirror 1 can belaid out to provide the additional current by increasing the emitter areato be a 1.5X multiple of the reference’s emitter area. Once again, we haveassumed ideal transistors. Let us consider the effect of finite forwardcurrent gain β on the accuracy of our current mirror. β is defined as Ic /Ib . A typical range of values is 100 < β < 400. Thus,for any current to flow in the collector, some current must be flowingin the base. If our circuit is based on a diode-connected transistor, thebase current will be subtracted from the collector current and an errorwill result. Figure 3.4a shows the current mirror provided with an idealFigure 3.4 Multiple transistor current mirror.reference current Iin . Since we now have a finite forward current gain,the currents flowing in the bases of Q1 and Q2 are also supplied by Iin .These currents reduce the amount of Iin that flows in the collector ofQ1. If we approximate the base currents of both Q1 and Q2 as equal,we have Ic (Q2) Iout = Ic (Q2) = Iin − 2 (3.3) β Q1’s base-emitter voltage will reflect the amount of collector currentflowing, and Q2 will mirror a current that is less than Iin . Figure 3.4b shows a circuit that reduces the error due to base current.Transistor Q3 acts as a buffer and provides the base current for Q1 andQ2. The emitter current for Q3 is then equal to 2Ic (Q1) IE (Q3) = Ib (Q1) + Ib (Q2) = (3.4) βThe base current of Q3 is then given as IE (Q3) 2Ic (Q1) Ib (Q3) = = (3.5) β ...