analog bicmos design practices and pitfalls phần 9

và vì vậy việc sử dụng các phân tích tín hiệu nhỏ cho giai đoạn phát đi theo sản lượng phải được xem xét cẩn thận. Ước tính hợp lý của cả hai đạt được điện áp và kháng đầu ra có thể thu được bằng cách sử dụng thiên vị hiện tại không hoạt động trong các phương trình miễn là các thay đổi điện áp đầu vào là vừa phải.
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analog bicmos design practices and pitfalls phần 9Figure 8.15 The power transistor Q1 is held “off” by Q2. However, atelevated temperatures, Q1 leakage current is excessive, turning on Q1, causingthe output current Io to exceed specifications.8.3.2 Temperature Turns On TransistorsCollector current increases with temperature. At low Vbe (250mV ), acollector current of a few nanoamperes is observed at room temperature.But at elevated temperatures (135◦ C ), collector currents in the hundredsof microamp range flow, causing circuit failure in spite of the low Vbe .This is due to the exponential dependence of saturation current Is ontemperature. The transistor Q2 in Figure 8.15 controls the power transistor Q1.When Q2 is on, it sinks Q1’s base current, holding Q1 off. The saturationresistance of Q2 is 50 Ohms. When sinking 5mA, its Vce is 0.25 V. Atroom temperature this holds Q1 off. Leakage current of about 6nA flowsin the off Q1. At elevated temperatures, the saturation resistance of Q2increases, but the current through it, Ib , may decrease. Here we assumethe voltage across Q2 does not change appreciably with temperature.It remains at 0.25 V. In spite of this low Vbe , Q2 begins to turn on atelevated temperatures. At elevated temperatures, the saturation current Is increases causingthe Q1 collector current Io to increase from nanoamps to hundreds ofmicroamps. Since Q1 is “off,” this constitutes circuit failure. Since Ic = Is exp(Vbe /VT ), where VT is the thermal voltage, at roomtemperature Q1 carries 100mA at Vbe = 0.68V . This corresponds toIs = 4E-13 A. With Vbe = 0.25V , the collector current for Q1 is 6.2nA. The saturation current Is is a function of the strongly temperature de-pendent quantity, intrinsic carrier concentration, ni . SPICE models thetemperature dependence of the saturation current Is using the followingFigure 8.16 A SPICE simulation showing Is is a nearly exponential func-tion of temperature.equation: XT I T2 qEg T2 exp − 1− Is (T2 ) = Is (T1 ) T1 KT2 T1 r T1 = 300◦ K . r T2 = 415◦ K = 135◦ C . The junction temperature is 10 degrees above the 125◦ C ambient. r Is (T1 ) = 4E-13. r The SPICE parameter (Is temperature effect exponent) XTI = 1.7. r The thermal voltage KT = 0.0259V at T = T1 (room tempera- ture). r The bandgap voltage Eg = 1.12V . At T2 = 415◦ K , Is has increased by a factor of 2.8E5 above the roomtemperature value to 0.11 µA. With Vbe held constant at 0.25 V, Ic in-creases to 119 µA. more than one-tenth of a milliamp. This representsa failure since Vbe is only 0.25 V, the transistor Q1 is designed to be OFF.Remedy The transistor Q2 has to be large enough to handle the leakage currentfrom Q1 at elevated temperatures.8.4 ComparatorsThis section discusses three failure modes for comparators. The first is“headroom” failure, where there is not enough voltage across the tran-sistor providing the bias current. The transistor saturates causing thecircuit to fail. In the second case, the allowable range of input voltagesis exceeded. The third is a case where charge stored in a Darlingtoninput causes an erroneous comparison.8.4.1 Headroom FailureComparator tail current is cut off due to insufficient voltage across thecurrent source. The two comparator modes look OK, but switching froma LOW output to a HIGH output fails.Example 1Figure 8.17 Logic level comparator. The circuit shown in Figure 8.17 is designed to act as a logic levelinput comparator. A LOW input turns P1 on and P2 off. With P2 off,current to the current mirror G2 is zero. This represents a HIGH to theI2L gate G3 . The output is LOW. When the input is HIGH, P1 is off,P2 is on, and the output is HIGH. Hysteresis is achieved by the currentmirror N1 and N2 . With P2 on, N1 and N2 turn on. N2 pulls the base of P2 to one Vbebelow the reference voltage of 1.9 V. That’s about 1.2 V. This low basevoltage snaps P2 to fully on. The circuit is shown with a LOW input. Trouble occurs because there is not enough headroom. When the volt-age across P3 is low, P3 saturates, current decreases, and the comparatorfails. With a zero input voltage P1 is on. P2 , N1 , and N2 are off. 28 µAflowing through the 100 K resistor from the current mirror P3 drives thebase of P2 to 2.8 volts. The emitters of P1 and P2 are at one Vbe (0.7 Vat room temperature). The base of P3 is one Vbe below V CC . That’sabout 2.6 V. When the input goes HIGH, P1 turns off. The emitters of P1 and P2attempt to rise to one Vbe above the base of P2 . That’s 2.8 + 0.7 = 3.5V at room temperature. However, there is not sufficient voltage acrossP3 to maintain ...