Bài giảng Computer Architecture: Chapter 2 - Prof. Jerry Breecher

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Bài giảng Computer Architecture: Chapter 2 - Prof. Jerry BreecherComputer Architecture Chapter 2 Instruction Sets Prof. Jerry Breecher CSCI 240 Fall 2003 Introduction2.1 Introduction2.2 Classifying Instruction Set Architectures2.3 Memory Addressing2.4 Operations in the Instruction Set2.5 Type and Size of Operands2.6 Encoding and Instruction Set2.7 The Role of Compilers2.8 The MIPS ArchitectureBonus Chap.2InstructionSets 2 IntroductionThe Instruction Set Architecture is that portion of the machine visible to the assembly level programmer or to the compiler writer. software instruction set hardware1. What are the advantages and disadvantages of various instruction set alternatives.2. How do languages and compilers affect ISA.3. Use the DLX architecture as an example of a RISC architecture. Chap.2InstructionSets 3 Classifying Instruction Set2.1 Introduction Architectures2.2 Classifying Instruction Set Architectures2.3 Memory Addressing2.4 Operations in the Instruction Set Classifications can be by:2.5 Type and Size of Operands2.6 Encoding and Instruction Set2.7 The Role of Compilers 1. Stack/accumulator/register2.8 The DLX Architecture 2. Number of memory operands. 3. Number of total operands. Chap.2InstructionSets 4 Instruction Set Basic ISA Architectures ClassesAccumulator: 1 address add A acc acc + mem[A] 1+x address addx A acc acc + mem[A + x]Stack: 0 address add tos tos + nextGeneral Purpose Register: ALU Instructions 2 address add A B EA(A) EA(A) + EA(B) can have two or 3 address add A B C EA(A) EA(B) + EA(C) three operands.Load/Store: 0 Memory load R1, Mem1 ALU Instructions can load R2, Mem2 have 0, 1, 2, 3 operands. add R1, R2 Shown here are cases of 0 and 1. 1 Memory add R1, Mem2 Chap.2InstructionSets 5Instruction Set Basic ISA Architectures Classes The results of different address classes is easiest to see with the examples here, all of which implement the sequences for C = A + B. Stack Accumulator Register Register (Register-memory) (load-store)Push A Load A Load R1, A Load R1, APush B Add B Add R1, B Load R2, BAdd Store C Store C, R1 Add R3, R1, R2Pop C Store C, R3Registers are the class that won out. The more registers on the CPU, the better. Chap.2InstructionSets 6Instruction Set Intel 80x86 Architectures Integer RegistersGPR0 EAX AccumulatorGPR1 ECX Count register, string, loopGPR2 EDX Data Register; multiply, divideGPR3 EBX Base Address RegisterGPR4 ESP Stack PointerGPR5 EBP Base Pointer – for base of stack seg.GPR6 ESI Index RegisterGPR7 EDI Index Register CS Code Segment Pointer SS Stack Segment Pointer DS Data Segment Pointer ES Extra Data Segment Pointer FS Data Seg. 2 GS Data Seg. 3PC EIP Instruction Counter Eflags Condition Codes Chap.2InstructionSets 7 Memory Addressing2.1 Introduction2.2 Classifying Instruction Set Architectures2.3 Memory Addressing2.4 Operations in the Instruction Set Sections Include:2.5 Type and Size of Operands2.6 Encoding and Instruction Set Interpreting Memory Addresses2.7 The Role of Compilers2.8 The DLX Architecture Addressing Modes Displacement Address Mode Immediate Address Mode Chap.2InstructionSets 8 Memory Interpreting MemoryAddressing AddressesWhat object is accessed as a function of the address and length?Objects have byte addresses – an address refers to the number of bytes counted from the beginning o ...