Bài giảng Computer Architecture: Chapter 8 - Prof. Jerry Breecher

Bài giảng Computer Architecture: Chapter 8 - MultiprocessorsShared Memory Architectures hướng đến trình bày các vấn đề về Introduction – the big picture; centralized Shared Memory Architectures. Cùng tìm hiểu và tham khảo nội dung thông tin tài liệu.
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Bài giảng Computer Architecture: Chapter 8 - Prof. Jerry BreecherComputer Architecture Chapter 8 Multiprocessors Shared Memory Architectures Prof. Jerry Breecher CSCI 240 Fall 2003 Chapter OverviewWe’re going to do only one section from this chapter, that part related to how caches from multiple processors interact with each other.8.1 Introduction – the big picture8.3 Centralized Shared Memory Architectures Chap.8Multiprocessors 2 The Big Picture: Where are Introduction We Now?8.1 Introduction The major issue is this:8.3 Centralized Shared Memory Architectures We’ve taken copies of the contents of main memory and put them in caches closer to the processors. But what happens to those copies if someone else wants to use the main memory data? How do we keep all copies of the data in synch with each other? Chap.8Multiprocessors 3The Multiprocessor Picture Processor/Memory Bus Example: Pentium System Organization PCI Bus I/O Busses Chap.8Multiprocessors 4Shared Memory Multiprocessor Processor Processor Processor Processor Registers Registers Registers Registers Caches Caches Caches Caches Memory Chipset •Memory: centralized with Uniform Memory Access time (“uma”) and bus interconnect, I/O Disk & other IO •Examples: Sun Enterprise 6000, SGI Challenge, Intel SystemPro Chap.8Multiprocessors 5 Shared Memory Multiprocessor• Several processors share one address space P P P – conceptually a shared memory – often implemented just like a Network/Bus multicomputer • address space distributed over private memories M• Communication is implicit Conceptual Model – read and write accesses to shared memory locations• Synchronization – via shared memory locations • spin waiting for non-zero – barriers Chap.8Multiprocessors 6 Message Passing Multicomputers• Computers (nodes) connected by a network – Fast network interface • Send, receive, barrier – Nodes not different than regular PC or workstation• Cluster conventional workstations or PCs with fast network – cluster computing – Berkley NOW Node – IBM SP2 P P P M M M Network Chap.8Multiprocessors 7 Large-Scale MP DesignsMemory: distributed with nonuniform memory access time (“numa”) and scalable interconnect (distributed memory) 100 cycles 40 cycles Low Latency High Reliability 1 cycle Chap.8Multiprocessors 8 Shared Memory Architectures8.1 Introduction In this section we will understand the8.3 Centralized Shared issues around: Memory Architectures • Sharing one memory space among several processors. • Maintaining coherence among several copies of a data item. Chap.8Multiprocessors 9Shared Memory Architectures The Problem of Cache Coherency CPU CPU CPU Cache Cache Cache A’ 100 A’ 550 A’ 100 B’ 200 B’ 200 B’ 200 Memory Memory Memory A 100 A 100 A 100 B 200 B 200 B 440 I/O I/O I/O Output of A gives 100 Input 440 to B a) Cache and memory b) Cache and memory c) Cache and memory coherent: A’ = A, B’ = B. incoherent: A’ ^= A. incoherent: B’ ^= B. Chap.8Multiprocessors 10Shared Memory Some Simple Definitions Architectures Mechanism How It Works Performance Coherency Issues Write modified Good, Can have problem ...