ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL

Phần 1: Đóng cửa sổ (không có sách hoặc các chú giải được) Câu hỏi 1 [25 điểm]: Một máy nhà nước được sử dụng trong một hệ thống điều khiển quá trình có 3 tiểu bang. Nó có một đồng hồ và một (hoạt động cao) không đồng bộ tín hiệu đặt lại, nhập vào một gọi là cảm biến và xuất ra một gọi là van. Sản lượng van cao ở trạng thái S1 hoặc S2. Các trạng thái tiếp theo / xuất bảng là:...
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ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL - Fall 2010 Final Exam – Verilog (6.00 to 8.30) SOLUTIONS This exam is in two parts. The first part is closed book (no books or notes allowed). • The second part is open book (books and notes are allowed). • Read each question carefully. Use a standard and consistent coding style. Try and answer each question - if you consider any question to be ambiguous then state any assumptions you make.NAME: ___________________________ECE Box: ________________________ECE574: VHDL and Verilog Modeling and Synthesis 1 12/08/10Part 1: Closed Book (No Books or Notes allowed)Question 1 [25 marks]: A state machine used in a process control system has 3 states. It hasa clock and an asynchronous (active high) reset signal, one input called sensor and one outputcalled valve. The valve output is high in state S1 or S2. The next state/output table is:Current State sensor valve 0 1 S0 S0 S1 0 S1 S1 S2 1 S2 S0 S0 1 S*Draw a state diagram of the state machine.Write a synthesizable description of this controller. Use a standard two always statementstyle. Describe the output logic using a separate assign statement.ECE574: VHDL and Verilog Modeling and Synthesis 2 12/08/10Question 2 [20 marks]: Write the Verilog synthesizable module description of a counterwith an asynchronous reset (active high) signal. The counter should count from 7 to 77 on anegative edge of the clock and then restart at 7.ECE574: VHDL and Verilog Modeling and Synthesis 3 12/08/10Question 3 [20 marks]: An FPGA running off its own local 100MHz oscillator is connectedto a GPS device in another system with its own clock. The GPS device generates a 1PPS (onepulse per second) signal that is high for approximately 10us in duration that it sends to theFPGA.It is necessary for the FPGA to generate a single 10ns pulse each time it detects the 1PPSpulse.Write a synthesizable module for the FPGA that will convert the 10us pulse from the GPSdevice clock domain into the 10ns pulse inside the FPGA. The start of the module descriptionis provided:module gps_pps ( input clk, input pps_long, output pps_short );ECE574: VHDL and Verilog Modeling and Synthesis 4 12/08/10Question 4 [35 marks]: Write a Verilog model of an SRAM memory device with thefollowing specifications:Address bus - 9 bitsData bus - 8 bitsActive low control signals: CE, OE, WERead operation (CE and OE valid):In the model, output the correct data only after an access time of tacc from OE and CE.Write operation (CE and WE valid - write data on the rising edge of WE)In the model check that the address bus is stable for taddr and the data bus is stable for tsetupbefore the rising edge of WE.If they do not meet these requirements then issue appropriate error messages.Use parameters for the access, address, and setup times with default times of 50, 70, and 25ns.Example solution shown on next page: minor variations are OK.ECE574: VHDL and Verilog Modeling and Synthesis 5 12/08/10ECE574: VHDL and Verilog Modeling and Synthesis 6 12/08/10Part 2: Open Book (Text book and Notes allowed).NAME: ___________________________ECE Box: ________________________Question 1 [30 marks]:A linear feedback shift register (LFSR) is a shift register whose input bit is a linear functionof its previous state.The only linear function of single bits is xor, thus it is a shift register whose input bit isdriven by the exclusive-or (xor) of some bits of the overall shift register value.The initial value of the LFSR is called the seed, and because the operation of the register isdeterministic, the stream of values produced by the register is completely determined by itscurrent (or previous) state. Likewise, because the register has a finite number of possiblestates, it must eventually enter a repeating cycle. However, an LFSR with a well-chosenfeedback function can produce a sequence of bits which appears random and which has avery long cycle.Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences,fast digital counters, and whitening sequences. Both hardware and software implementationsof LFSRs are common.The bit positions that affect the next state are called the taps. In the diagram the taps are[16,14,13,11]. The rightmost bit of the LFSR is called the output bit. The taps are XORdsequentially with the output bit and then fed back into the leftmost bit. The sequence of bitsin the rightmost position is called the output stream.The state ACE1 hex shown will be followed by 5670 hex.Design a synthesizable module to implement the LFSR in the diagram.Assume it is driven by a positive edge triggered clk.Assume it has an asynchronous reset to load it with the initial seed value ACE1 hex.The output should be connected to the output of the 16th register.ECE574: VHDL and Verilog Modeling and Synthesis 7 12/08/10Question 2 [35 marks]: Design a state machine that is used as a security safe controller. Ithas four push-button switches called ‘A’, ‘B’, ‘C’, ‘D’ and one output called ‘LOCK’. It willopen the safe when the four switches are pressed in the sequence “B,D,A,C”. If an incorrectco ...