Finite State Machine Datapath Design, Optimization, and Implementation

Calculating maximum clock, improving design performance, finite state machine with datapath design, embedded memory usage in finite state machine with datapath designs,... As the main contents of the document "Finite State Machine Datapath Design, Optimization, and Implementation". Invite you to consult.
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Finite State Machine Datapath Design, Optimization, and ImplementationFinite State MachineDatapath Design, Optimization,and ImplementationCopyright © 2008 by Morgan & ClaypoolAll rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted inany form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotationsin printed reviews, without the prior permission of the publisher. Finite State Machine Datapath Design, Optimization, and Implementation Justin Davis and Robert Reese www.morganclaypool.com ISBN: 1598295292 paperback ISBN: 9781598295290 paperback ISBN: 1598295306 ebook ISBN: 9781598295306 ebook DOI: 10.2200/S00087ED1V01Y200702DCS014 A Publication in the Morgan & Claypool Publishers series SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS #14 Lecture #14 Series Editor: Mitchell Thornton, Southern Methodist University Series ISSN ISSN 1932-3166 print ISSN 1932-3174 electronicFinite State MachineDatapath Design, Optimization,and ImplementationJustin DavisRaytheon Missile SystemsRobert ReeseMississippi State UniversitySYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS #14iv ABSTRACT Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. KEYWORDS: Verilog, datapath, scheduling, latency, throughput, timing, pipelining, memories, FPGA, flowgraph v Table of ContentsChapter 1 – Calculating Maximum Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Chapter 2 – Improving design performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Chapter 3 – Finite State Machine with Datapath (FSMD) Design . . . . . . . . . . . . . . . . . . . . . . . . 35Chapter 4 – Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83vi vii Table of FiguresFigure 1.1: Inverter propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 1.2: AND gate propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 1.3: Glitches caused by propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 1.4: XOR gate architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 1.5: D-type flip-flop input options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 1.6: Relative setup and hold time timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 1.7: Sequential circuit for propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 1.8: Calculating adjusted setup/hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 1.9: Adjusted setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 1.10: Board-level schematic to compute maximum clock frequency . . . . . . . . . . . . . . . . . 15Figure 2.1: Adding an output register to the sequential circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 2.2: Adding input registers to the sequential circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 2.3: Operation of a Delay Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 2.4: Board-level schematic to compute maximum clock frequency . . . . . . . . . . . . . . . . . . 30Figure 3.1: Saturating Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 3.2: Unsigned Saturating Adder (8-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 3.3: Implementation for 1-F operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 3.4: Multiplication of an 8-bit color operand by 9-bit blend ...