Logic Synthesis With Verilog HDL part 2

[ Team LiB ] 14.3 Verilog HDL Synthesis For the purpose of logic synthesis, designs are currently written in an HDL at a register transfer level (RTL). The term RTL is used for an HDL description style that utilizes a combination of data flow and behavioral constructs.
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Logic Synthesis With Verilog HDL part 2[ Team LiB ]14.3 Verilog HDL SynthesisFor the purpose of logic synthesis, designs are currently written in an HDL at a registertransfer level (RTL). The term RTL is used for an HDL description style that utilizes acombination of data flow and behavioral constructs. Logic synthesis tools take theregister transfer-level HDL description and convert it to an optimized gate-level netlist.Verilog and VHDL are the two most popular HDLs used to describe the functionality atthe RTL level. In this chapter, we discuss RTL-based logic synthesis with Verilog HDL.Behavioral synthesis tools that convert a behavioral description into an RTL descriptionare slowly evolving, but RTL-based synthesis is currently the most popular designmethod. Thus, we will address only RTL-based synthesis in this chapter.14.3.1 Verilog ConstructsNot all constructs can be used when writing a description for a logic synthesis tool. Ingeneral, any construct that is used to define a cycle-by-cycle RTL description isacceptable to the logic synthesis tool. A list of constructs that are typically accepted bylogic synthesis tools is given in Table 14-1. The capabilities of individual logic synthesistools may vary. The constructs that are typically acceptable to logic synthesis tools arealso shown. Table 14-1. Verilog HDL Constructs for Logic Synthesis Construct Keyword or Description Notes Typeports input, inout, outputparameters parametermodule moduledefinitionsignals and wire, reg, tri Vectors are allowedvariablesinstantiation module instances, E.g., mymux m1(out, i0, i1, s); E.g., nand primitive gate instances (out, a, b);functions and function, task Timing constructs ignoredtasksprocedural always, if, then, else, case, initial is not supported casex, casezprocedural begin, end, named blocks, Disabling of named blocks allowedblocks disabledata flow assign Delay information is ignoredloops for, while, forever, while and forever loops must contain @(posedge clk) or @(negedge clk)Remember that we are providing a cycle-by-cycle RTL description of the circuit. Hence,there are restrictions on the way these constructs are used for the logic synthesis tool. Forexample, the while and forever loops must be broken by a @ (posedge clock) or @(negedge clock) statement to enforce cycle-by-cycle behavior and to preventcombinational feedback. Another restriction is that logic synthesis ignores all timingdelays specified by # construct. Therefore, pre- and post-synthesis Verilogsimulation results may not match. The designer must use a description style thateliminates these mismatches. Also, the initial construct is not supported by logicsynthesis tools. Instead, the designer must use a reset mechanism to initialize the signalsin the circuit.It is recommended that all signal widths and variable widths be explicitly specified.Defining unsized variables can result in large, gate-level netlists because synthesis toolscan infer unnecessary logic based on the variable definition.14.3.2 Verilog OperatorsAlmost all operators in Verilog are allowed for logic synthesis. Table 14-2 is a list of theoperators allowed. Only operators such as === and !== that are related to x and z are notallowed, because equality with x and z does not have much meaning in logic synthesis.While writing expressions, it is recommended that you use parentheses to group logic theway you want it to appear. If you rely on operator precedence, logic synthesis tools mightproduce an undesirable logic structure. Table 14-2. Verilog HDL Operators for Logic Synthesis Operator Type Operator Symbol Operation PerformedArithmetic * multiply / divide + add - subtract % modulus + unary plus - unary minusLogical ! logical negation && logical and || logical orRelational > greater than < less than >= greater than or equal Shift >> right shift >> arithmetic right shift If arithmetic operators are used, each arithmetic operator is implemented in terms ofarithmetic hardware blocks available to the logic synthesis tool. A 1-bit full adder isimplemented below.assign {c_out, sum} = a + b + c_in;Assuming that the 1-bit full adder is available internally in the logic synthesis tool, theabove assign statement is often interpreted by logic synthesis tools as follows:If a multiple-bit adder is synthesized, the synthesis tool will perform optimization and thedesigner might get a result that looks different from the above figure.If a conditional operator ? is used, a multiplexer circuit is inferred.assign out = (s) ? i1 : i0;It frequently translates to the gate-level representation shown in Figure 14-3. Figure 14-3. Multiplexer DescriptionThe if-else statementSingle if-else statements translate to multiplexers where the control signal is the signal orvariable in the if clause.if(s) out = i1;else out = i0;The above statement will frequently translate to the gate-level description shown inFigure ...