Model-Based Design for Embedded Systems- P26

Model-Based Design for Embedded Systems- P26:The unparalleled flexibility of computation has been a key driver and featurebonanza in the development of a wide range of products across a broadand diverse spectrum of applications such as in the automotive aerospace,health care, consumer electronics, etc.
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Model-Based Design for Embedded Systems- P26726 Index specialization piecewise constant derivatives discrete functional category, 507 (PCD), 396 hybrid category, 509–510 time steps, 398 multi-viewpoint composition, model-based design, 383–384 512–515 modeling safety/probabilistic categories, discrete dynamics, 389–390 510–512 Lipschitz continuous, 390 semantic atoms, 507 non-determinism, 391 system architecture, 512 trajectories, 390–391 timed category, 507–509 rapidly-exploring random trees wrapper mechanism, 512 (RRTs)Hierarchical event streams (HESs) algorithm, 408–409 inner and output event streams, 71–73 hybrid distance, 410–411 structure, 71 iterations, 409–410 system analysis, 70–71 simulations, 409HRC, see Heterogeneous rich component test generation (HRC) state machines algorithm, steps, 425Hybrid approach cases and executions, 423–424 advantages and disadvantages, 35–36 continuous inputs, 422 basic block coverage-guided sampling, pipeline modeling, 40–43 425–426 principles, 39 discrete transitions, 422–423 static cycle calculation, 40 state coverage strategies, cycle prediction, dynamic correction 421–422 branch prediction, 43 test coverage, 424–425 cache analysis blocks, 44 testing, 411–412 cache model, 44 cycle calculation code, 45 I instruction cache, 43 IBIS, see Interconnection bus for objectives, 35 integrated sensors software tasks, 46–47 ICAP, see Internal configuration access SystemC code annotation, 38–40 port task switches, 46 IContinu, see Continuous domain WCET/BCET value, back-annotation interface, model advantages, 38 IDiscrete, see Discrete domain interface, architecture, 36–37 model instruction set, 37–38 Inertial measurement unit (IMU), 698,Hybrid automata 702, 703, 716, 717 exhaustive verification InitializeTA method, 469, 471 abstraction, 403–404 Input/output buffer (IOB), 368 autonomous linear systems, 398 Integrated multi-technology systems finite syntactic representation, abstraction levels, 608, 609 397–398 application, 622–631 linear inequalities, 397 CMOS transistor, 603–604 linear systems, 398–401 design productivity gap, 606 nonlinear systems, 401–403 ENIAC, 604–605 nontrivial differential equations, heterogeneous design methods, 396–397 639–640 Index 727 integrated optical interconnect BPT, 634–636 delay analysis, 632–634 link sizing method, 634 gate area analysis, 632, 633 power vs. interconnect length, 634, link specification set, 631 636 optical point-to-point link static and dynamic power, 637–638 synthesis, 623, 626–630 total power vs. interconnect performance metrics and length, 637 specification sets, 630–631 simulation and synthesis power analysis, 634–638 functional model, 622–623 simulation and synthesis, 622–623, optical device parameters, 623, 626 624–625 structural model, 622–623 simulation conditions, 632 UML class diagram, 623–625 synthesis procedures, 631 Verilog-AMS, 623 ITRS and design technology, 606–607 simulation conditions, 632 RuneII project synthesis procedures, 631 abstraction levels, 612–618 Interconnection bus for integrated design technology, 608, 610 sensors (IBIS) goals, 610–611 communications, 699 posteriori evaluation, 612 drivers, 708–711 priori generation, 612 sensors, 714–715 SoC/SiP design flow, 610–611 structure, 711, 714 system-level and physical-level Internal configuration access port phases, 611–612 (ICAP), 358, 370–372 UML/XML implementation, International technology roadmap for 618–622 semiconductors (ITRS), 520 several economic sectors, 604 Inverse discrete cosine transformation silicon and system complexity, 604, (IDCT) accelerator 606 address map and interfacing code, systems on chip (SoC), 603–604 222–223Integrated optical interconnect interfacing code and interrupt delay analysis, 632–634, 635 handler code, 223–224 gate area analysis, 632, 633 macroblock decoding tasks, 221–222 link specification set, 631 ...