Sequential Verulog Topics part 9

PLI Interface provides a set of C interface routines to read, write, and extract information about the internal data structures of the design. Designers can write their own system tasks
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Sequential Verulog Topics part 913.5 SummaryIn this chapter, we described the Programming Language Interface (PLI) forVerilog. The following aspects were discussed: • PLI Interface provides a set of C interface routines to read, write, and extract information about the internal data structures of the design. Designers can write their own system tasks to do various useful functions. • PLI Interface can be used for monitors, debuggers, translators, delay calculators, automatic stimulus generators, dump file generators, and other useful utilities. • A user-defined system task is implemented with a corresponding user- defined C routine. The C routine uses PLI library calls. • The process of informing the simulator that a new user-defined system task is attached to a corresponding user C routine is called linking. Different simulators handle the linking process differently. • User-defined system tasks are invoked like standard Verilog system tasks, e.g., $hello_verilog(); . The corresponding user C routine hello_verilog is executed whenever the task is invoked. • A design is represented internally in a Verilog simulator as a big data structure with sets for objects. PLI library routines allow access to the internal data structures. • Access (acc) routines and utility (tf) routines are two types of PLI library routines. • Utility routines represent the first generation of Verilog PLI. Utility routines are used to pass data back and forth across the boundary of user C routines and the original Verilog design. Utility routines start with the prefix tf_. Utility routines do not interact with object handles. • Access routines represent the second generation of Verilog PLI. Access routines can read and write information about a particular object from/to the design. Access routines start with the prefix acc_. Access routines are used primarily across the boundary of user C routines and internal data representation. Access routines interact with object handles. • Value change link (VCL) is a special category of access routines that allow monitoring of objects in a design. A consumer routine is executed whenever the monitored object value changes. • Verilog Procedural Interface (VPI) routines represent the third generation of Verilog PLI. VPI routines provide a superset of the functionality of acc_ and tf_ routines. VPI routines are not covered in this book.Programming Language Interface is a very broad area of study. Thus, only thebasics of Verilog PLI are covered in this chapter. Designers should consult theIEEE Standard Verilog Hardware Description Language document for details ofPLI.[ Team LiB ][ Team LiB ]13.6 ExercisesRefer to Appendix B, List of PLI Routines and IEEE Standard Verilog HardwareDescription Language document, for a list of PLI access and utility routines, theirfunction, and usage. You will need to use some PLI library calls that were notdiscussed in this chapter. 1: Write a user-defined system task, $get_in_ports, that gets full hierarchical names of only the input ports of a module instance. Hierarchical module instance name is the input to the task (Hint: Use the C routine in Example 13-2 as a reference). Link the task into the Verilog simulator. Find the input ports of the 1-bit full adder defined in Example 5-7 on page 75. 2: Write a user-defined system task, $count_and_gates, which counts the number of and gate primitives in a module instance. Hierarchical module instance name is the input to the task. Use this task to count the number of and gates in the 4-to-1 multiplexer in Example 5-5. 3: Create a user-defined system task, $monitor_mod_output, that finds out all the output signals of a module instance and adds them to a monitoring list. The line Output signal has changed should appear whenever any output signal of the module changes value. (Hint: Use VCL routines.) Use the 2- to-1 multiplexer in Example 13-1. Add output signals to the monitoring list by using $monitor_mod_output. Check results by applying stimulus.[ Team LiB ][ Team LiB ]14.1 What Is Logic Synthesis?Simply speaking, logic synthesis is the process of converting a high-leveldescription of the design into an optimized gate-level representation, given astandard cell library and certain design constraints. A standard cell library can havesimple cells, such as basic logic gates like and, or, and nor, or macro cells, such asadders, muxes, and special flip-flops. A standard cell library is also known as thetechnology library. It is discussed in detail later in this chapter.Logic synthesis always existed even in the days of schematic gate-level design, butit was always done inside the designers mind. The designer would first understandthe architectural description. Then he would consider design constraints such astiming, area, testability, and power. The designer would partition the design intohigh-level blocks, draw them on a piece of paper or a computer terminal, anddescribe the functionality of the circuit. This was the high-level description.Finally, each block would be implemented on a hand-drawn schematic, using thecells available in the standard cell library. The last step was the most complexprocess in the design flow and required several time-consuming design iterationsbefore an optimized gate-level representation that met all design constraints wasobtained. Thus, the designers mind was used as the logic synthesis tool, asillustrated in Figure 14-1. Figure 14-1. Designers Mind as the Logic Synthesis ToolThe advent of computer-aided logic synthesis tools has automated the process ofconverting the high-level description to lo ...