USB Complete fourth- P46

USB Complete fourth- P46:This book focuses on Windows programming for PCs, but other computersand operating systems also have USB support, including Linux and AppleComputer’s Macintosh. Some real-time kernels also support USB.
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USB Complete fourth- P46Chapter 18 &KHHGTGPVKCN CPF &KHHGTGPVKCN When transferring data, the two states on the bus are Differential 0 and Differ- ential 1. A Differential 0 exists when D+ is a logic low and D- is a logic high. A Differential 1 exists when D+ is a logic high and D- is a logic low. Chapter 19 has details about the voltages. The Differential 0/1s don’t translate directly into zero and one data states but instead indicate either a change in logic level, no change in logic level, or a bit stuff, as explained later in this chapter. 5KPINGGPFGF The Single-ended 0 (SE0) state occurs when both D+ and D- are logic low. The bus uses the SE0 state when entering the EOP, Disconnect, and Reset states. 5KPINGGPFGF The complement of SE0 is the Single-ended 1 (SE1). This state occurs when both D+ and D- are logic high. This is an invalid bus state and should never occur except as specified in the USB battery-charging specification. &CVC , CPF &CVC - In addition to the Differential 0 and Differential 1 states, which are defined by voltages on the lines, USB also defines two Data bus states, J and K. These are defined by whether the bus state is Differential 0 or Differential 1 and the speed of the cable segment: $WU 5VCVG &CVC 5VCVG .QY 5RGGF (WNN 5RGGF Differential 0 Data J Data K Differential 1 Data K Data J Defining the J and K states in this way makes it possible to use one terminology to describe an event or logic state even though the voltages on low- and full-speed lines differ. For example, a Start-of-Packet state exists when the bus changes from Idle to the K state. On a full-speed segment, the state occurs when D- becomes more positive than D+, while on a low-speed segment, the state occurs when D+ becomes more positive than D-.426 Packets on the Bus+FNGIn the Idle state, no drivers are active. On a full-speed segment, D+ is more pos-itive than D-, while on a low-speed segment, D- is more positive than D+.Shortly after device attachment, a hub determines whether a device is low orfull speed by checking the voltages on the Idle bus at the device’s port.4GUWOGWhen a device is in the Suspend state, a Data K state at the device’s port signi-fies a resume from Suspend.5VCTVQH2CEMGVThe Start-of-Packet (SOP) bus state exists when the lines change from the Idlestate to the K data state. Every transmitted low- or full-speed packet begins withan SOP.PFQH2CEMGVThe End-of-Packet (EOP) state exists when a receiver has been in the SE0 statefor at least one bit time followed by a Data J state for at least one bit time. Areceiver may optionally accept a shorter minimum time for the Data J state. Atthe driver, an SE0 is approximately two bit widths. Every transmitted low- orfull-speed packet ends with an EOP.&KUEQPPGEVA downstream port is in the Disconnect state when an SE0 has persisted for atleast 2.5 µs.%QPPGEVA downstream port enters the Connect state when the bus has been in the Idlestate for at least 2.5 µs and no more than 2.0 ms.4GUGVWhen an SE0 has lasted for 10 ms, the device must be in the Reset state. Adevice may enter the Reset state after an SE0 of at least 2.5 µs. A full-speeddevice that is capable of high-speed communications performs the high-speedhandshake during the Reset state. 427Chapter 18 On exiting the Reset state, a device must be operating at its correct speed and must respond to communications directed to the default address (00h).*KIJ 5RGGF $WU 5VCVGU Many of the high-speed bus states correspond to states for low and full speed, but a few are unique to high speed, and some low/full-speed states have no equivalents at high speed. *KIJURGGF &KHHGTGPVKCN CPF &KHHGTGPVKCN The two bus states that exist when transferring high-speed data are High-speed Differential 0 and High-speed Differential 1. As with low and full speeds, a High-speed Differential 0 exists when D+ is a logic low and D- is a logic high, and a High-speed Differential 1 exists when D+ is a logic high and D- is a logic low. The voltage requirements differ at high speed, however, and high speed has additional requirements for AC differential levels. *KIJURGGF &CVC , CPF &CVC - The definitions for High-speed Data J and Data K states are identical to those for full-speed J and K. $WU 5VCVG &CVC 5VCVG JKIJ URGGF Differential 0 High-speed Data K Differential 1 High-speed Data J %JKTR , CPF %JKTR - The Chirp J and Chirp K bus states are present only during the high-speed detection handshake. The handshake occurs when a USB 2.0 hub has placed a downstream bus segment in the Reset state. In a Chirp J, D+ is more positive than D-, and in a Chirp K, D- is more positive than D+. A high-speed device must use full speed on attaching to the bus. The high-speed detection handshake enables a high-speed device to tell a USB 2.0 hub that the device supports high speed and to transition to high-speed com- munications. As Chapter 4 explained, shortly after detecting device attachment, a device’s hub places a device’s port and bus segment in the Reset state. When a high-speed-capable device detects the Reset, the device places its line in the428 Packets on the BusChirp K state for ...