Useful Modeling Techniques part 3

[ Team LiB ] 9.5 Useful System Tasks In this section, we discuss the system tasks that are useful for a variety of purposes in Verilog. We discuss system tasks [1] for file output, displaying hierarchy, strobing, random number generation, memory initialization,
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Useful Modeling Techniques part 3[ Team LiB ]9.5 Useful System TasksIn this section, we discuss the system tasks that are useful for a variety of purposes inVerilog. We discuss system tasks [1] for file output, displaying hierarchy, strobing,random number generation, memory initialization, and value change dump.[1] Other system tasks such as $signed and $unsigned used for sign conversion are notdiscussed in this book. For details, please refer to the IEEE Standard Verilog HardwareDescription Language document.9.5.1 File OutputOutput from Verilog normally goes to the standard output and the file verilog.log. It ispossible to redirect the output of Verilog to a chosen file.Opening a fileA file can be opened with the system task $fopen.Usage: $fopen(); [2][2] The IEEE Standard Verilog Hardware Description Language document providesadditional capabilities for $fopen. The $fopen syntax mentioned in this book is adequatefor most purposes. However, if you need additional capabilities, please refer to the IEEEStandard Verilog Hardware Description Language document.Usage: = $fopen();The task $fopen returns a 32-bit value called a multichannel descriptor.[3] Only one bit isset in a multichannel descriptor. The standard output has a multichannel descriptor withthe least significant bit (bit 0) set. Standard output is also called channel 0. The standardoutput is always open. Each successive call to $fopen opens a new channel and returns a32-bit descriptor with bit 1 set, bit 2 set, and so on, up to bit 30 set. Bit 31 is reserved.The channel number corresponds to the individual bit set in the multichannel descriptor.Example 9-9 illustrates the use of file descriptors.[3] The IEEE Standard Verilog Hardware Description Language document provides amethod for opening up to 230 files by using a single-channel file descriptor. Please referto it for details.Example 9-9 File Descriptors//Multichannel descriptorinteger handle1, handle2, handle3; //integers are 32-bit values//standard output is open; descriptor = 32h0000_0001 (bit 0 set)initialbegin handle1 = $fopen(file1.out); //handle1 = 32h0000_0002 (bit 1 set) handle2 = $fopen(file2.out); //handle2 = 32h0000_0004 (bit 2 set) handle3 = $fopen(file3.out); //handle3 = 32h0000_0008 (bit 3 set)endThe advantage of multichannel descriptors is that it is possible to selectively write tomultiple files at the same time. This is explained below in greater detail.Writing to filesThe system tasks $fdisplay, $fmonitor, $fwrite, and $fstrobe are used to write to files.[4]Note that these tasks are similar in syntax to regular system tasks $display, $monitor, etc.,but they provide the additional capability of writing to files.[4] The IEEE Standard Verilog Hardware Description Language document providesmany additional capabilities for file output. The file output system tasks mentioned in thisbook are adequate for most digital designers. However, if you need additional capabilitiesfor file output, please refer to the IEEE Standard Verilog Hardware DescriptionLanguage document.Systems tasks for reading files are also provided by the IEEE Standard Verilog HardwareDescription Language. These system tasks include $fgetc, $ungetc, $fgetc, $fscanf,$sscanf, $fread, $ftell, $fseek, $rewind, and $fflush. However, most digital designers donot need these capabilities frequently. Therefore, they are not covered in this book. If youneed to use the file reading capabilities, please refer to the IEEE Standard VerilogHardware Description Language document.We will consider only $fdisplay and $fmonitor tasks. Usage: $fdisplay(, p1, p2 ..., pn); $fmonitor(, p1, p2,..., pn);p1, p2, …, pn can be variables, signal names, or quoted strings.A file_descriptor is amultichannel descriptor that can be a file handle or a bitwise combination of file handles.Verilog will write the output to all files that have a 1 associated with them in the filedescriptor. We will use the file descriptors defined in Example 9-9 to illustrate the use ofthe $fdisplay and $fmonitor tasks.//All handles defined in Example 9-9//Writing to filesinteger desc1, desc2, desc3; //three file descriptorsinitialbegin desc1 = handle1 | 1; //bitwise or; desc1 = 32h0000_0003 $fdisplay(desc1, Display 1);//write to files file1.out & stdout desc2 = handle2 | handle1; //desc2 = 32h0000_0006 $fdisplay(desc2, Display 2);//write to files file1.out & file2.out desc3 = handle3 ; //desc3 = 32h0000_0008 $fdisplay(desc3, Display 3);//write to file file3.out onlyendClosing filesFiles can be closed with the system task $fclose.Usage: $fclose();//Closing Files$fclose(handle1);A file cannot be written to once it is closed. The corresponding bit in the multichanneldescriptor is set to 0. The next $fopen call can reuse the bit.9.5.2 Displaying HierarchyHierarchy at any level ...