VHDL for Efficient Testbenches

Various efficient VHDL behavioural modelling language constructsare available to generate stimulus to test a VHDL model, e.g.,• for loop• defining stimulus array & indexing the array to apply stimulus• reading stimulus data directly from a fileMessages can also be added to testbenchRemember that this type of testbench / behavioural VHDL code is notintended for logic synthesis, and normally cannot be synthesised !Refer to muxAndDecEx1 lab files muxAndDecEx1_TB.vhd for theseexamples of testbench coding...
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VHDL for Efficient Testbenches VHDL for Efficient Testbenches using muxAndDecEx1 combinational logic example Dr Fearghal MorganVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p1 VHDL For Efficient Testbenches (TBs) Learning outcomes On completion of this module, you should be able to : Apply stimulus using Explicit stimulus application using single process -- detailed in muxAndDecEx1 multiple processes -- course material For loop Array FileIO Generate message output during simulation Presentation also introduces VHDL functions and their definition in the IEEE VHDL libraries VHDL VariablesVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p2 muxAndDecEx1 Testbench & Simulation Visualise the test bench structure muxAndDecEx1 decOut decOutVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p3 Basic muxAndDecEx1 TestbenchVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p4 Basic muxAndDecEx1 Testbench Simulation WaveformVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p5 Alternative Stimulus GenerationVarious efficient VHDL behavioural modelling language constructsare available to generate stimulus to test a VHDL model, e.g.,• for loop• defining stimulus array & indexing the array to apply stimulus• reading stimulus data directly from a fileMessages can also be added to testbenchRemember that this type of testbench / behavioural VHDL code is notintended for logic synthesis, and normally cannot be synthesised !Refer to muxAndDecEx1 lab files muxAndDecEx1_TB.vhd for theseexamples of testbench codingVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p6 Stimulus Generation using for loopmuxAndDecEx1 example : use for loop to create 8 stimulus setsConvert integer loop index to a signal vector using VHDL function.VHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p7for loop Syntax Use Edit > language templates > VHDL > for loop statement For statement is synthesisable as long as the loop has a fixed range For statement is commonly used in testbench (behavioural) modelsVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p8 Functions in VHDLFunctions (and procedures) are used widely in VHDLConversion functions are common for example: to convert from integer type (easily manipulated using for loops) to a vector of signals, use the function CONV_STD_LOGIC_VECTOR(integerName, vectorWidth) This function converts integer value to vector of width vectorWidthMany conversion functions existFunctions can reduce VHDL model complexityVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p9 Conversion Functions in VHDL Use Edit > language templates > VHDL > conversion functions Use Viewing VHDL function models work library (compiled project files) IEEE libraries In main modelsim window, select ‘library’ workspace to view libraries content Edit (using right mouse button) to open library Search to view function detailVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p11Viewing ieee.std_logic_arith library inModelsimVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p12 Conversion Functions in VHDLUse Edit > language templates > VHDL > conversion functionsFunctiondefined in arith Function overloading :library Specific function used depends on argument typesLibrary packagemust be Functions are applied using a VHDLreferenced in assignment, e.g., Stimulus Generation using Array• muxAndDecEx1: define two 8 element 4-bit arrays• Use for loop to index each array element and assign mux input values• No type conversion is required VHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p14 Use of VHDL Variables for Testbench Stimuli • Always consider using variables to generate stimulus patterns in TBs • Variables (very similar to signals) can only be defined and used within a process (not accessible outside process) • Variable can be used to efficiently define stimulus data inside process before assigning the stimulus to a signal • Variables can simplify data processingVHDL for efficient testbenches www.appliedVHDL.com Applied VHDL Training Course, Dr Fearghal Morgan, V2007.1 p15 File based Stimulus Generation ...