Ebook ASIC and FPGA verification: A guide to component modeling – Part 1

Ebook ASIC and FPGA verification: A guide to component modeling – Part 1 includes contents: Chapter 1 introduction to board-level verification, chapter 2 tour of a simple model, chapter 3 VHDL packages for component models, chapter 4 an introduction to SDF, chapter 5 anatomy of a vital model, chapter 6 modeling delays, chapter 7 vital tables, chapter 8 timing constraints.
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Ebook ASIC and FPGA verification: A guide to component modeling – Part 1