Ebook ASIC and FPGA verification: A guide to component modeling – Part 2

Ebook ASIC and FPGA verification: A guide to component modeling – Part 2 includes contents: Chapter 9 modeling components with registers, chapter 10 conditional delays and timing constraints, chapter 11 negative timing constraints, chapter 12 timing files and backannotation, chapter 13 adding timing to your RTL code, chapter 14 modeling memories, chapter 15 considerations for component modeling, chapter 16 modeling component-centric features, chapter 17 testbenches for component models.
Nội dung trích xuất từ tài liệu:
Ebook ASIC and FPGA verification: A guide to component modeling – Part 2