ECE 551 ModelSim Tutorial
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In this tutorial, you will learn how to setup a ModelSim project, compile your Verilog files, correct compilation errors, and perform design debugging using ModelSim. The example design used within this tutorial is simple Synchronous Serial Port (SSP) that contains both a send and receive module.
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ECE 551 ModelSim TutorialECE 551 ModelSim TutorialBrian Hickmann, Michael Morrow(co-opted & tweaked for Hoffman/Nalamalpu)Dept of ECE, UW-MadisonIn this tutorial, you will learn how to setup a ModelSim project, compile your Verilog files, correctcompilation errors, and perform design debugging using ModelSim. The example design used within thistutorial is simple Synchronous Serial Port (SSP) that contains both a send and receive module. It has asimple 3-wire interface: Port Name Function SerData Bi-directional data line used for both sending and receiving Recv_nTran Input that indicates if we are receiving (1) or transmitting (0) StartOp Input that indicates that an operation should be performedThe design of this unit is broken into a number of separate modules: Module Name Function ssp Top-level module which instantiates all of the below sub-modules receive Contains the shift register and state machine for the receiver transmit Contains the shift register and state machine for the transmitter busint Contains the logic to control the three wire serial interfaceThe tutorial also contains testbenches for the receive, transmit, and ssp modules.The ModelSim Tutorial must be run on a Linux workstation using your CAE account in order to use thelatest release of ModelSim (version 6.3).IMPORTANT NOTEIt is critical to remember that Verilog is NOT a software language. Verilog is used to describe hardware.While ModelSim may provide the ability to step through the code or insert breakpoints, this is NOT whatactually happens when the hardware is operating. In reality, hardware is inherently parallel, with eachtransistor or gate continuously providing an output signal based upon its input signals.For example, in software, if there is an “if (flag) a = b&c else a = b|c” statement, only one branch of thestatement is actually executed. However, if HDL code has an “if-else” statement, hardware must becreated for both branches if the value of “flag” isn’t constant. When we synthesize to hardware, both anAND gate and an OR gate are created with “b” and “c” as inputs, and a multiplexer is created to choosethe result based on the value of “flag”, and the output of the multiplexer is sent to “a”. Both gates arealways present and operating continuously, regardless of the value of “flag”. Stepping through the code,however, will make it appear as if only one of the branches is executed. To make the simulation moreefficient, the simulator will only perform calculations and event scheduling when necessary. Since itknows the value of “flag”, it will only schedule the event relating to the input of the multiplexer that isactive.1 Tutorial SetupDirectory and File SetupIn your root directory, create an ece551 directory: %> mkdir ece551Change directory to the ece551 directory: %> cd ece551Copy all the tutorial files to your current directory: %> cp –r ~ehoffman/public_html/tutorials/modelsim .Change directory to your tutorial directory: %> cd modelsim/tutorialStart ModelSim %> newver vsimWhen you start ModelSim for the first time, a pop-up box will appear (possibly after a short delay) as inFigure 1-1. You should check the Don’t Show… box and then close the window. You need to usenewver vsim because CAE (Computer Aided Engineering) also supports an older version of ModelSimthat some research students use. The version that we will use for the course offers more complete supportfor Verilog 2001 and an improved user interface. Figure 1-1: Important Information pop-up Figure 1-2: ModelSim default window.Now that ModelSim is open, you should see a default window similar to that inFigure 1-2. There are a few things to note about the window. In the lower left hand corner, it says which indicates that there is no current Verilog or VHDL simulation. There is aWorkspace on the left hand side of the window that currently contains only the Library tab. On thebottom of the window is a command line area that can be used either to issue commands, or view theoutputs of commands run through the GUI.Many (although not all) operations performed through the menus will also echo into the command line ortranscript area, so you can learn the command-line operation as you go. Knowing the command-linecommands is important, for example, if you want to write a script to perform a set of simulations. Helpfor each command-line command is available by entering help on the command line.2 Creating ProjectsCreate a New Proj ...
Nội dung trích xuất từ tài liệu:
ECE 551 ModelSim TutorialECE 551 ModelSim TutorialBrian Hickmann, Michael Morrow(co-opted & tweaked for Hoffman/Nalamalpu)Dept of ECE, UW-MadisonIn this tutorial, you will learn how to setup a ModelSim project, compile your Verilog files, correctcompilation errors, and perform design debugging using ModelSim. The example design used within thistutorial is simple Synchronous Serial Port (SSP) that contains both a send and receive module. It has asimple 3-wire interface: Port Name Function SerData Bi-directional data line used for both sending and receiving Recv_nTran Input that indicates if we are receiving (1) or transmitting (0) StartOp Input that indicates that an operation should be performedThe design of this unit is broken into a number of separate modules: Module Name Function ssp Top-level module which instantiates all of the below sub-modules receive Contains the shift register and state machine for the receiver transmit Contains the shift register and state machine for the transmitter busint Contains the logic to control the three wire serial interfaceThe tutorial also contains testbenches for the receive, transmit, and ssp modules.The ModelSim Tutorial must be run on a Linux workstation using your CAE account in order to use thelatest release of ModelSim (version 6.3).IMPORTANT NOTEIt is critical to remember that Verilog is NOT a software language. Verilog is used to describe hardware.While ModelSim may provide the ability to step through the code or insert breakpoints, this is NOT whatactually happens when the hardware is operating. In reality, hardware is inherently parallel, with eachtransistor or gate continuously providing an output signal based upon its input signals.For example, in software, if there is an “if (flag) a = b&c else a = b|c” statement, only one branch of thestatement is actually executed. However, if HDL code has an “if-else” statement, hardware must becreated for both branches if the value of “flag” isn’t constant. When we synthesize to hardware, both anAND gate and an OR gate are created with “b” and “c” as inputs, and a multiplexer is created to choosethe result based on the value of “flag”, and the output of the multiplexer is sent to “a”. Both gates arealways present and operating continuously, regardless of the value of “flag”. Stepping through the code,however, will make it appear as if only one of the branches is executed. To make the simulation moreefficient, the simulator will only perform calculations and event scheduling when necessary. Since itknows the value of “flag”, it will only schedule the event relating to the input of the multiplexer that isactive.1 Tutorial SetupDirectory and File SetupIn your root directory, create an ece551 directory: %> mkdir ece551Change directory to the ece551 directory: %> cd ece551Copy all the tutorial files to your current directory: %> cp –r ~ehoffman/public_html/tutorials/modelsim .Change directory to your tutorial directory: %> cd modelsim/tutorialStart ModelSim %> newver vsimWhen you start ModelSim for the first time, a pop-up box will appear (possibly after a short delay) as inFigure 1-1. You should check the Don’t Show… box and then close the window. You need to usenewver vsim because CAE (Computer Aided Engineering) also supports an older version of ModelSimthat some research students use. The version that we will use for the course offers more complete supportfor Verilog 2001 and an improved user interface. Figure 1-1: Important Information pop-up Figure 1-2: ModelSim default window.Now that ModelSim is open, you should see a default window similar to that inFigure 1-2. There are a few things to note about the window. In the lower left hand corner, it says which indicates that there is no current Verilog or VHDL simulation. There is aWorkspace on the left hand side of the window that currently contains only the Library tab. On thebottom of the window is a command line area that can be used either to issue commands, or view theoutputs of commands run through the GUI.Many (although not all) operations performed through the menus will also echo into the command line ortranscript area, so you can learn the command-line operation as you go. Knowing the command-linecommands is important, for example, if you want to write a script to perform a set of simulations. Helpfor each command-line command is available by entering help on the command line.2 Creating ProjectsCreate a New Proj ...
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