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EURASIP Journal on Applied Signal Processing 2003:13, 1328–1334 c 2003 Hindawi Publishing CorporationInterleaved Convolutional Code and Its Viterbi Decoder ArchitectureJun Jin KongDepartment of Electrical and Computer Engineering, University of Minnesota, 200 Union Street, Minneapolis, MN 55455, USA Email: jjkong@ece.umn.eduKeshab K. ParhiDepartment of Electrical and Computer Engineering, University of Minnesota, 200 Union Street, Minneapolis, MN 55455, USA Email: parhi@ece.umn.edu Received 4 February 2003 and in revised form 17 June 2003 We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code. The state-parallel architecture uses as...
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EURASIP Journal on Applied Signal Processing 2003:13, 1328–1334 c 2003 Hindawi Publishing
