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EURASIP Journal on Applied Signal Processing 2003:6, 530–542 c 2003 Hindawi Publishing CorporationAn FPGA Implementation of (3, 6)-Regular Low-Density Parity-Check Code DecoderTong ZhangDepartment of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180, USA Email: tzhang@ecse.rpi.eduKeshab K. ParhiDepartment of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA Email: parhi@ece.umn.edu Received 28 February 2002 and in revised form 6 December 2002 Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel...
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EURASIP Journal on Applied Signal Processing 2003:6, 530–542 c 2003 Hindawi Publishing
