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Hardware and Computer Organization- P5:Today, we often take for granted the impressive array of computing machinery that surrounds usand helps us manage our daily lives. Because you are studying computer architecture and digitalhardware, you no doubt have a good understanding of these machines, and you’ve probably writtencountless programs on your PCs and workstations.
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Hardware and Computer Organization- P5:Chapter 5 timer = 5 seconds; NS = yellow; while ( timer != 0) wait; timer = 20 seconds; NS = red; EW = green; while ( timer != 0) wait; timer = 5 seconds; EW = yellow; while ( timer != 0) wait; } }Notice that there is a new wrinkle in this problem. The times are different. We are nominally in theN/S state for 20 seconds, and then, if there is an EW car waiting, we have to transition for5 seconds through a yellow light before turning on EW green for 20 seconds.The statement, while(1), is often used in embedded systems to identify the portion of the pro-gram code that will run forever. Once the system, such as a printer, is initialized, the printer runsforever (or until you turn off the power).Let’s look at the state transition diagram, shown in Figure 5.11. The state of the EW traffic sen-sor is an input to our algorithm and it can modify the behavior of the system. We can representthis condition by using the fact that there are two possible paths for the state machine to take onceit is in the state NS GRN/EW RED. As long as neither of the E/W sensors detects a waiting car,the traffic control algorithm will remain in thisstate. However, if a waiting car is detected at the NS RED NS REDend of the time interval for NS GRN, then the EW GRN EW YEL 20 SEC 5 SECstate machine transitions to the state NS YEL/EW RED. Once in this state, the algoritm mustsequence through NS RED/EW GRN and NSRED/EW YEL before it re-enters the state NSGRN/EW RED. There are no possible inputs inthese other states that can change the sequence. NS YEL WT = 1 NS GRN WT = 0 EW RED or EW RED and ET = 1 ET = 0 5 SEC 20 SEC Figure 5.11: State transition diagram for the traffic intersection. 102 Introduction to State MachinesAgain, assuming we could take care of the time requirements, you could easily change the pseudocode of this algorithm to a real program in C or C++. Of course, we’d need to supply an I/O portto drive the lights and a timer mechanism, but these are simple implementation details. Let’s take abrief diversion from our algorithmic state machine design and introduce a new concept (just whenyou thought it was safe to go back into the water, bang!). Figure 5.12 shows us the state of theoutputs represented as a timing diagram. This timing diagram shows us the state of the input sig-nals that control the lights versus time. Notice in Figure 5.12 that our horizontal axis is calibratedin 5 second ticks. This just shows that the outputs can only change on the 5-second clock ticks.The timing diagram of Figure 5.12 represents an alternative view of the system. In fact, this iswhat the controller outputs to the traffic light power circuits would look like on the screen of alogic analyzer. This kind of view is significant because it introduces us to another important con-cept, the idea of the states of the system represented as a set of state vectors. The state vectors arejust the combination of all of the possible states of the inputs and outputs that our system might bein. Thus, if you create a table of all of the vectors, then you have an alternative way of represent-ing all of the possible states of the system. Figure 5.13 is a representation of the timing diagram ofFigure 5.12, but now represented as a state vector set. NS RED 1 0 NS YELLOW 1 0 NS GREEN 1 0 EW RED 1 0 EW YELLOW 1 0 EW GREEN 1 0 0 5 10 15 20 25 30 35 40 45 50 Time, seconds Figure 5.12: Traffic light sequence represented as a timing diagram.At each clock transition, the state of the system can be described by the binary vector set or bythe hexadecimal vector set. We have to be a bit careful here because the hexadecimal represen-tation shouldn’t be confused with a number. It’s not. It is a colle ...