Hardware and Computer Organization- P6:

Hardware and Computer Organization- P6:Today, we often take for granted the impressive array of computing machinery that surrounds usand helps us manage our daily lives. Because you are studying computer architecture and digitalhardware, you no doubt have a good understanding of these machines, and you’ve probably writtencountless programs on your PCs and workstations.
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Hardware and Computer Organization- P6:Chapter 6In this section, we will start from A single bit memory cellthe D-flop as an individual device DATAand see how we can interconnect IN/OUTmany of them to form a memoryarray. In order to see how data Dcan be written to the memory and W Qread from the memory along thesame signal path (although not at CLKthe same instant in time), considerFigure 6.10.The black box is just a slightly D-FF core without OE Tri-state buffersimplified version of the basic S, R and QD flip-flop. We’ve eliminated the Figure 6.10 Schematic representation of a single bit of memory.S, R inputs and Q output. The The tri-state buffer on the output of the cell controls when thedark gray box is the tri-state buf- Q output may be connected to the bus.fer, which is controlled by a separate OE (output enable) input. When OE is HIGH, the tri-statebuffer is disabled, and the Q output of the memory cell is isolated (Hi-Z state) from the data lines(DATA I/O line). However, the Data line is still connected to the D input of the cell, so it is pos-sible to write data to the cell, but the new data written to the cell is not immediately visible tosomeone trying to read from the cell until the tri-state buffer is enabled. When we combine thebasic FF cell with the tri-state buffer, we have all that we need to make a 1-bit memory cell. This isindicated by the light gray box surrounding the two elements that we’ve just discussed.The write signal is a bit misleading, so we should discuss it. We know that data is written into theD-FF on the rising edge of a pulse, which is indicated by the up-arrow on the write pulse (W) inFigure 6.10. So why is the write signal, W, written as if it was an active low signal? The reason isthat we normally keep the write signal in a 1 state. In order to accomplish a write operation, theW must be brought low, and then returned high again. It is the low-to-high transition that accom-plishes the actual data write operation, but since we must bring the write line to a low state in orderto accomplish the actual writing of the data, we consider the write signal to be active low. Also,you should infer from this discussion that you would never activate the W line and the OE lines atthe same time. Either you bring W low and keep OE high, or vice versa. They never are low at thesame time. Now, let’s return to our analysis of the memory array.We’ll take another step forward in complexity and build a memory out of tri-state devices andD-flops. Figure 6.11 shows a simple (well maybe not so simple) 16-bit memory organized as four,4-bit nibbles. Each storage bit is a miniature D-flop that also has a tri-state buffer circuit inside ofit so that we can build a bus system with it.Each row of four D-FF’s has two common control lines that provide the clock function (write)and the output enable function for placing data onto the I/O bus. Notice how the correspondingbit position from each row is physically tied to the same wire. This is why we need the tri-statecontrol signal, OE, on each bit cell (D-FF). For example, if we want to write data into row 2 ofD-FF’s the data must be place on the DB0 through DB3 from the outside device and the W2 signal 132 Bus Organization and Memory Designmust go high to store DB0 DB1 DB2 DB3the data. Also, to writedata into the cells, the A0OE signal must be kept D Q D Q D Q D Qin the HIGH state in A1 (W0)D0..D3 CLK OE CLK OE CLK OE CLK ...