Bài giảng Computer Organization and Architecture: Chapter 5

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Bài giảng Computer Organization and Architecture: Chapter 5William StallingsComputer Organizationand Architecture6th EditionChapter 5Internal MemorySemiconductor Memory TypesSemiconductor Memory• RAM —Misnamedasallsemiconductormemoryisrandom access —Read/Write —Volatile —Temporarystorage —StaticordynamicMemory Cell OperationDynamic RAM• Bitsstoredaschargeincapacitors• Chargesleak• Needrefreshingevenwhenpowered• Simplerconstruction• Smallerperbit• Lessexpensive• Needrefreshcircuits• Slower• Mainmemory• Essentiallyanalogue —LevelofchargedeterminesvalueDynamic RAM StructureDRAM Operation• Addresslineactivewhenbitreadorwritten —Transistorswitchclosed(currentflows)• Write —Voltagetobitline – Highfor1lowfor0 —Thensignaladdressline – Transferschargetocapacitor• Read —Addresslineselected – transistorturnson —Chargefromcapacitorfedviabitlinetosense amplifier – Compareswithreferencevaluetodetermine0or1 —CapacitorchargemustberestoredStatic RAM• Bitsstoredason/offswitches• Nochargestoleak• Norefreshingneededwhenpowered• Morecomplexconstruction• Largerperbit• Moreexpensive• Doesnotneedrefreshcircuits• Faster• Cache• Digital —UsesflipflopsStating RAM StructureStatic RAM Operation• Transistorarrangementgivesstablelogicstate• State1 —C1high,C2low —T1T4off,T2T3on• State0 —C2high,C1low —T2T3off,T1T4on• AddresslinetransistorsT5T6isswitch• Write–applyvaluetoB&complimenttoB• Read–valueisonlineBSRAM v DRAM• Bothvolatile —Powerneededtopreservedata• Dynamiccell —Simplertobuild,smaller —Moredense —Lessexpensive —Needsrefresh —Largermemoryunits• Static —Faster —CacheRead Only Memory (ROM)• Permanentstorage —Nonvolatile• Microprogramming(seelater)• Librarysubroutines• Systemsprograms(BIOS)• FunctiontablesTypes of ROM• Writtenduringmanufacture —Veryexpensiveforsmallruns• Programmable(once) —PROM —Needsspecialequipmenttoprogram• Read“mostly” —ErasableProgrammable(EPROM) – ErasedbyUV —ElectricallyErasable(EEPROM) – Takesmuchlongertowritethanread —Flashmemory – ErasewholememoryelectricallyOrganisation in detail• A16Mbitchipcanbeorganisedas1Mof16bit words• Abitperchipsystemhas16lotsof1Mbitchip withbit1ofeachwordinchip1andsoon• A16Mbitchipcanbeorganisedasa2048x 2048x4bitarray —Reducesnumberofaddresspins – Multiplexrowaddressandcolumnaddress – 11pinstoaddress(211=2048) – Addingonemorepindoublesrangeofvaluessox4capacityRefreshing• Refreshcircuitincludedonchip• Disablechip• Countthroughrows• Read&Writeback• Takestime• SlowsdownapparentperformanceTypical 16 Mb DRAM (4M x 4)PackagingModuleOrganizationModule Organization (2)Error Correction• HardFailure —Permanentdefect• SoftError —Random,nondestructive —Nopermanentdamagetomemory• DetectedusingHammingerrorcorrectingcode