A high throughput, low latency 105 Gbps four-pipeline stage AES

This paper present a high-throughput, low latency 4-pipeline stages architecture of AES with efficient throughput per resource (Mbps/slice). The proposed implementation achieves a high throughput of 105.7 Gbps with an efficiency of 31.48 Mbps/slice. In comparison to state-of-the-art works, our design surpasses the majority of existing designs in terms of throughput and latency.
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A high throughput, low latency 105 Gbps four-pipeline stage AES